1. Field of the Invention
This invention relates to the field of VLSI (very large scale integration) circuit design, and particularly to methods and apparatus for determining the voltage response as a function of time, at a remote terminal within such a circuit, using a known voltage input.
2. Description of Prior Art
VLSI circuit chips are today commonplace in microprocessors and the like. They are designed by teams of engineers who, presented with a particular requirement, analytically design the proposed chip and prepare a layout drawing. The latter macroscopically presents the extremely complex pattern of components and interconnects which, when photo-etched, doped and deposited onto the silicon matrix, will collectively constitute the finished chip, which may include millions of microscopic components, all interconnected according to the design.
The sequence of manufacturing steps required to produce such a VLSI chip in quantity can easily be correspondingly complex. Thus, from initial design to setup of the manufacturing line, introduction of a new VLSI chip is an extremely expensive process, and not to be initiated lightly.
A major technical consideration underlying any new chip design is the maximum clock frequency at which the chip will operate in situ. If the frequency must, for the particular application, be greater than that at which a chip according to the particular design can operate, failure of the chip to function properly--or literal failure of the chip--can be the result.
It is important, therefore, in the process of designing a new chip or in implementing its manufacture, to determine, if possible, the maximum clock frequency at which the chip will operate. Obviously, if the maximum operating frequency can be determined at the analytical design point, before a significant investment in the manufacturing line has been made, a great deal of money can be saved by redesign, if the chip, when manufactured, will not operate properly at the frequency required. And even if, at a subsequent point in the process, the design must be altered--or even abandoned and replaced with an entirely new approach--this might ultimately prove to be a prudent investment.
Additionally, although such cost savings can be easily appreciated in respect to a VLSI chip with millions of components and interconnects, the potential savings which can thus be realized in the case of even a relatively simple IC, incorporating only thousands of components, can likewise be quite significant.
Accordingly, it is necessary to determine, at the preliminary design phase, if possible, the extent to which the proposed chip--of whatever level of complexity--can be driven at or above the required clock frequency. This requires analysis of the time delay--from selected input to selected output points--of a signal input to the chip. I.e., it is necessary to determine the voltage response as a function of time.
The source of considerable transmission delay are the interconnects, themselves. Although it would be ideal if interconnects were loss-free--i.e., totally devoid of impedance--this is, unfortunately, not the case in the real world. Each interconnect does, in fact, demonstrate a degree of resistance, capacitance and (to a considerably lesser degree) inductance. While such impedance might be almost negligible in a single interconnect, even an extremely small value will have a significant effect on the maximum response speed of the circuit. Collectively, the delay caused by possibly millions of such interconnects will have a profound effect on reducing the maximum operating frequency.
As mentioned in the Provisional Application, the methods which have previously been applied to determine voltage response characteristics of IC interconnects as functions of time fall into three categories: (a) segment-based simulation; (b) pure time-domain response computation and (c) analysis in a transform domain.
An example of the first is the URC simulation method, described therein, which conceptually divides an interconnect of given length into a finite sequence of segments, each having determinable values of the principal parasitics (i.e., resistance (R) and capacitance (C)) per unit length. The resulting equivalent circuit is then simulated to obtain signal response in the time domain.
As discussed in the Provisional Application, another pure time-domain method has been applied to the very special case of a step input to a finite, open-ended (i.e., infinite) load RC line. And even this solution is obtained by application of the questionable assumption that voltage response, as a function of position and time, is separable into time-dependent and position-dependent functions.
The problem is that even in the simplest source and load impedance cases, and with the application of often-unwarranted assumptions, computations of voltage response purely in the time domain involve very difficult, numerical solutions of complex differential and integral equations. However, applying the above third category solution, i.e., by transforming the problem out of the time domain--particularly, by transform into the Laplace domain--these differential and integral equations become considerably more straightforward linear equations, which are solvable in closed form. Once the solution is found, it can be returned to the time domain by a single inverse Laplace transform.
The first step in the prior art expression of this latter approach has been to calculate an approximation of the transfer function applicable to the input signal, which can then be employed to determine the transform-domain (and, thus, the time-domain) voltage response at the selected output point. But such a transfer function can only be determined and used in a few very simple cases.
What is needed, then, is a method of determining voltage response through a finite RC line, which can be performed analytically--i.e., in closed form, by transformation outside the time domain--with only a single inverse transformation into the time domain for the ultimate determination of voltage response as a function of time, which can be employed in a realistic range of source and load impedances.